The search functionality is under construction.

Author Search Result

[Author] Yoshikazu MIYANAGA(35hit)

21-35hit(35hit)

  • VLSI Implementation of a Scalable Pipeline MMSE MIMO Detector for a 44 MIMO-OFDM Receiver

    Shingo YOSHIZAWA  Hirokazu IKEUCHI  Yoshikazu MIYANAGA  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E94-A No:1
      Page(s):
    324-331

    MIMO-OFDM performs signal detection on a subcarrier basis which requires high speed computation in MIMO detection due to its large computational cost. Conventional designs in a MIMO detector increase processing time in proportion to the number of subcarriers and have difficulty in real-time processing for large numbers of subcarriers. A complete pipeline MMSE MIMO detector presented in our previous work can provide high speed computation. However, it tends to be excessive in a circuit scale for small numbers of subcarriers. We propose a new scalable architecture to reduce circuit scale by adjusting the number of iterative operations according to various types of OFDM system. The proposed detector has reduced circuit area to about 1/2 to 1/7 in the previous design with providing acceptable latency time.

  • New PAPR Reduction in an OFDM System Using Hybrid of PTS-CAPPR Methods with GA Coded Side Information Technique

    Chusit PRADABPET  Shingo YOSHIZAWA  Yoshikazu MIYANAGA  Kobchai DEJHAN  

     
    PAPER-Communication Theory and Systems

      Vol:
    E92-A No:11
      Page(s):
    2830-2836

    In this paper, we propose a new PAPR reduction by using the hybrid of partial transmit sequences (PTS) and cascade adaptive peak power reduction (CAPPR) methods with side information (SI) technique coded by genetic algorithm (GA). These methods are used in an Orthogonal Frequency Division Multiplexing (OFDM) system. The OFDM employs orthogonal sub-carriers for data modulation. These sub-carriers unexpectedly present a large peak to average power ratio (PAPR) in some cases. A proposed reduction method realizes both the advantages of PTS and CAPPR at the same time. In order to obtain the optimum condition on PTS for PAPR reduction, a quite large calculation cost is demanded and thus it is impossible to obtain the optimum PTS in a short time. In the proposed method, by using the pseudo-optimum condition based on a GA coded SI technique, the total calculation cost becomes drastically reduced. In simulation results, the proposed method shows the improvement on PAPR and also reveals the high performance on bit error rate (BER) of an OFDM system.

  • New Error Resilience Technique Using Adaptive FMO and Intra Refresh for H.264 Video Transmission

    Tien HUU VU  Supavadee ARAMVITH  Yoshikazu MIYANAGA  

     
    PAPER-Digital Signal Processing

      Vol:
    E94-A No:8
      Page(s):
    1647-1655

    In this paper, we propose an error resilience scheme for wireless video coding based on adaptive flexible macroblock ordering (FMO) and intra refresh. An FMO explicit map is generated frame-by-frame by using prior information. This information involves estimated locations of guard and burst sections in the channel and estimated effect of error propagation (EEP) from the previous frame to the current frame. In addition, the role of the current frame in propagating an error to the next frame is also considered. A suitable intra refresh rate which is adaptive to the channel state is used to reduce the dependence between frames and thus can stop the EEP. The results in experiments show that the proposed method gains some improvements in terms of peak signal-to-noise rate (PSNR) as compared with some other methods that have not considered the channel condition and the error propagation in generating an FMO map.

  • Parallel VLSI Architecture for Multi-Layer Self-Organizing Cellular Network

    Yoshikazu MIYANAGA  Koji TOCHINAI  

     
    PAPER-Neural Networks and Chips

      Vol:
    E76-C No:7
      Page(s):
    1174-1181

    This paper proposes a multi-layer cellular network in which a self-organizing method is implemented. The network is developed for the purpose of data clustering and recognition. A multi-layer structure is presented to realize the sophisticated combination of several sub-spaces which are spanned by given input characteristic data. A self-organizing method is useful for evaluating the set of clusters for input data without a supervisor. Thus, using these techniques this network can provide good clustering ability as an example for image/pattern data which have complicated and structured characteristics. In addition to the development of this algorithm, this paper also presents a parallel VLSI architecture for realizing the mechanism with high efficiency. Since the locality can be kept among all processing elements on every layer, the system is easily designed without large global data communication.

  • Connectivity Modeling Analysis in Flight-Path Based Aviation Ad Hoc Networks

    Thi Xuan My NGUYEN  Yoshikazu MIYANAGA  Chaiyachet SAIVICHIT  

     
    PAPER

      Vol:
    E94-B No:6
      Page(s):
    1606-1616

    In this paper, we propose a framework of connectivity analysis for aviation ad hoc networks on flight paths. First, a general analytical connectivity model for the common one-dimensional ad hoc network is newly developed. Then it is applied for modeling the connectivity of ad hoc networks among aircraft along flight paths where aircraft arrival process follows a Poisson distribution. Connectivity is expressed in terms of connectedness probability of two nodes in the network, connected distance, and network coverage extension factor. An exact closed form derivation of connectedness probability is proposed. The radical effect of mobility on the network connectedness of aircraft over a single flight path is analyzed. The network connectedness probability depends on node density and node distribution, which are derived from node arrival rate and node velocity. Based on these results, the proposed model is extended to the practical case of paths with multi-velocity air traffic classes. Using this model, the critical values of system parameters for the network of aircraft with certain connectivity requirements can be derived. It helps to evaluate network extension capability under the constraints of various system parameters.

  • Tunable Wordlength Architecture for a Low Power Wireless OFDM Demodulator

    Shingo YOSHIZAWA  Yoshikazu MIYANAGA  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E89-A No:10
      Page(s):
    2866-2873

    We present a low power architecture that dynamically controls wordlengths in a wireless OFDM demodulator. Finding the optimum wordlength for digital circuit systems is difficult because the trade-off between the hardware cost and system performance is not conclusive. Actual circuit systems have large wordlengths at the circuit design level to avoid calculation errors caused by a lack of dynamic range. This indicates that power dissipation can still be reduced under better conditions. We propose a tunable wordlength architecture that dynamically changes its own wordlength according to the communication environment. The proposed OFDM demodulator measures error vector magnitudes (EVMs) from de-modulated signals and tunes the wordlength to satisfy the required quality of communication by monitoring the EVM performance. The demodulator can reduce dissipated energy by a maximum of 32 and 24% in AWGN and multipath fading channels.

  • A Low Power Tone Recognition for Automatic Tonal Speech Recognizer

    Jirabhorn CHAIWONGSAI  Werapon CHIRACHARIT  Kosin CHAMNONGTHAI  Yoshikazu MIYANAGA  Kohji HIGUCHI  

     
    PAPER

      Vol:
    E96-A No:6
      Page(s):
    1403-1411

    This paper proposes a low power tone recognition suitable for automatic tonal speech recognizer (ATSR). The tone recognition estimates fundamental frequency (F0) only from vowels by using a new magnitude difference function (MDF), called vowel-MDF. Accordingly, the number of operations is considerably reduced. In order to apply the tone recognition in portable electronic equipment, the tone recognition is designed using parallel and pipeline architecture. Due to the pipeline and parallel computations, the architecture achieves high throughput and consumes low power. In addition, the architecture is able to reduce the number of input frames depending on vowels, making it more adaptable depending on the maximum number of frames. The proposed architecture is evaluated with words selected from voice activation for GPS systems, phone dialing options, and words having the same phoneme but different tones. In comparison with the autocorrelation method, the experimental results show 35.7% reduction in power consumption and 27.1% improvement of tone recognition accuracy (110 words comprising 187 syllables). In comparison with ATSR without the tone recognition, the speech recognition accuracy indicates 25.0% improvement of ATSR with tone recogntion (2,250 training data and 45 testing words).

  • Optimizing and Scheduling DSP Programs for High Performance VLSI Designs

    Frederico Buchholz MACIEL  Yoshikazu MIYANAGA  Koji TOCHINAI  

     
    PAPER

      Vol:
    E75-A No:10
      Page(s):
    1191-1201

    The throughput of a parallel execution of a Digital Signal Processing (DSP) algorithm is limited by the iteration bound, which is the minimum period between the start of consecutive iterations. It is given by T=max (Ti/Di), where Ti and Di are the total time of operations and the number of delays in loop i, respectively. A schedule is said rate-optimal if its iteration period is T. The throughput of a DSP algorithm execution can be increased by reducing the Ti's, which can be done by taking as many operations as possible out of loops without changing the semantic of the calculation. This paper presents an optimization technique, called Loop Shrinking, which reduces the iteration bound this way by using commutativity, associativity and distributivity. Also, this paper presents a scheduling method, called Period-Driven Scheduling, which gives rate-optimal schedules more efficiently than existing approaches. An implementation of both is then presented for a system in development by the authors. The system shows reduction in the iteration bound near or equal to careful hand-tunning, and hardware-optimal designs in most of the cases.

  • Low-Power Dynamic MIMO Detection for a 4×4 MIMO-OFDM Receiver

    Nozomi MIYAZAKI  Shingo YOSHIZAWA  Yoshikazu MIYANAGA  

     
    PAPER-Digital Signal Processing

      Vol:
    E97-A No:1
      Page(s):
    306-312

    This paper describes low-power dynamic multiple-input and multiple-output (MIMO) detection for a 4×4 MIMO-orthogonal frequency-division multiplexing (MIMO-OFDM) receiver. MIMO-OFDM systems achieve high-speed and large capacity communications. However, they impose high computational cost in MIMO detection when separating spatially multiplexed signals and they consume vast amounts of power. We propose low-power dynamic MIMO detection that controls detection speed according to wireless environments. The power consumption is reduced by dynamic voltage and frequency scaling (DVFS) that controls the operating voltage and clock frequency in the MIMO detector. We implemented dynamic MIMO detection in a pipelined minimum mean square error (MMSE) MIMO detector that we developed in our previous work. A power saving of 92% was achieved under lowest clock frequency mode conditions.

  • An Adaptive Method Analyzing Analytic Speech Signals

    Eisuke HORITA  Yoshikazu MIYANAGA  Koji TOCHINAI  

     
    PAPER

      Vol:
    E77-A No:5
      Page(s):
    800-803

    An adaptive method analyzing analytic speech signals is proposed in this paper. The method decreases the errors of finite precision on calculation in a method with real coefficients. It is shown from the results of experiments that the proposed method is more useful than adaptive methods with real coefficients.

  • Multi-clustering Network for Data Classification System

    Rafiqul ISLAM  Yoshikazu MIYANAGA  Koji TOCHINAI  

     
    PAPER-Digital Signal Processing

      Vol:
    E80-A No:9
      Page(s):
    1647-1654

    This paper presents a new multi-clustering network for the purpose of intelligent data classification. In this network, the first layer is a self-organized clustering layer and the second layer is a restricted clustering layer with a neighborhood mechanism. A new clustering algorithm is developed in this system for the efficiently use of parallel processors. This parallel algorithm enables the nodes of this network to be independently processed in order to minimize data communication load among processors. Using the parallel processors, the quite low calculation cost can be realized among the conventional networks. For example, a 4-processor parallel computing system has shown its ability to reduce the time taken for data classification to 26.75% of a single processor system without declining its performance.

  • An Architecture for Real-Time Retinex-Based Image Enhancement and Haze Removal and Its FPGA Implementation Open Access

    Dabwitso KASAUKA  Kenta SUGIYAMA  Hiroshi TSUTSUI  Hiroyuki OKUHATA  Yoshikazu MIYANAGA  

     
    PAPER

      Vol:
    E102-A No:6
      Page(s):
    775-782

    In recent years, much research interest has developed in image enhancement and haze removal techniques. With increasing demand for real time enhancement and haze removal, the need for efficient architecture incorporating both haze removal and enhancement is necessary. In this paper, we propose an architecture supporting both real-time Retinex-based image enhancement and haze removal, using a single module. Efficiently leveraging the similarity between Retinex-based image enhancement and haze removal algorithms, we have successfully proposed an architecture supporting both using a single module. The implementation results reveal that just 1% logic circuits overhead is required to support Retinex-based image enhancement in single mode and haze removal based on Retinex model. This reduction in computation complexity by using a single module reduces the processing and memory implications especially in mobile consumer electronics, as opposed to implementing them individually using different modules. Furthermore, we utilize image enhancement for transmission map estimation instead of soft matting, thereby avoiding further computation complexity which would affect our goal of realizing high frame-rate real time processing. Our FPGA implementation, operating at an optimum frequency of 125MHz with 5.67M total block memory bit size, supports WUXGA (1,920×1,200) 60fps as well as 1080p60 color input. Our proposed design is competitive with existing state-of-the-art designs. Our proposal is tailored to enhance consumer electronic such as on-board cameras, active surveillance intrusion detection systems, autonomous cars, mobile streaming systems and robotics with low processing and memory requirements.

  • Design of Time-Varying ARMA Models and Its Adaptive Identification

    Yoshikazu MIYANAGA  Eisuke HORITA  Jun'ya SHIMIZU  Koji TOCHINAI  

     
    INVITED PAPER

      Vol:
    E77-A No:5
      Page(s):
    760-770

    This paper introduces some modelling methods of time-varying stochastic process and its linear/nonlinear adaptive identification. Time-varying models are often identified by using a least square criterion. However the criterion should assume a time invariant stochastic model and infinite observed data. In order to adjust these serious different assumptions, some windowing techniques are introduced. Although the windows are usually applied to a batch processing of parameter estimates, all adaptive methods should also consider them at difference point of view. In this paper, two typical windowing techniques are explained into adaptive processing. In addition to the use of windows, time-varying stochastic ARMA models are built with these criterions and windows. By using these criterions and models, this paper explains nonlinear parameter estimation and the property of estimation convergence. On these discussions, some approaches are introduced, i.e., sophisticated stochastic modelling and multi-rate processing.

  • Open Domain Continuous Filipino Speech Recognition: Challenges and Baseline Experiments

    Federico ANG  Rowena Cristina GUEVARA  Yoshikazu MIYANAGA  Rhandley CAJOTE  Joel ILAO  Michael Gringo Angelo BAYONA  Ann Franchesca LAGUNA  

     
    PAPER-Speech and Hearing

      Vol:
    E97-D No:9
      Page(s):
    2443-2452

    In this paper, a new database suitable for HMM-based automatic Filipino speech recognition is described for the purpose of training a domain-independent, large-vocabulary continuous speech recognition system. Although it is known that high-performance speech recognition systems depend on a superior speech database used in the training stage, due to the lack of such an appropriate database, previous reports on Filipino speech recognition had to contend with serious data sparsity issues. In this paper we alleviate such sparsity through appropriate data analysis that makes the evaluation results more reliable. The best system is identified through its low word-error rate to a cross-validation set containing almost three hours of unknown speech data. Language-dependent problems are discussed, and their impact on accuracy was analyzed. The approach is currently data driven, however it serves as a competent baseline model for succeeding future developments.

  • Effects of Channel Features on Parameters of Genetic Algorithm for MIMO Detection

    Kazi OBAIDULLAH  Constantin SIRITEANU  Shingo YOSHIZAWA  Yoshikazu MIYANAGA  

     
    PAPER-Digital Signal Processing

      Vol:
    E96-A No:10
      Page(s):
    1984-1992

    Genetic algorithm (GA) is now an important tool in the field of wireless communications. For multiple-input/multiple-output (MIMO) wireless communications system employing spatial multiplexing transmission, we evaluate the effects of GA parameters value on channel parameters in fading channels. We assume transmit-correlated Rayleigh and Rician fading with realistic Laplacian power azimuth spectrum. Azimuth spread (AS) and Rician K-factor are selected according to the measurement-based WINNER II channel model for several scenarios. Herein we have shown the effects of GA parameters and channel parameters in different WINNER II scenarios (i.e., AS and K values) and rank of the deterministic components. We employ meta GA that suitably selects the population (P), generation (G) and mutation probability (pm) for the inner GA. Then we show the cumulative distribution function (CDF) obtain experimentally for the condition number C of the channel matrix H. It is found that, GA parameters depend on the channel parameters, i.e., GA parameters are the functions of the channel parameters. It is also found that for the poorer channel conditions smaller GA parameter values are required for MIMO detection. This approach will help to achieve maximum performance in practical condition for the lower numerical complexity.

21-35hit(35hit)